An investigation of the utility of a new semiconductor fabrication technology as a local silicon-on-insulator (SOI) fabrication method is motivated by the need for a new low-temperature, cost-effective solution to current and near-future fabrication obstacles of semiconductor devices as outlined in the International Technology Roadmap for Semiconductors (ITRS)[1]. Several references[2][3][4][5][6][7][8][9][10] have recorded recent and current SOI fabrication methods and goals. The basic technology of solid-metal-mediated epitaxy (SMME)[11][12] allows various device components to be fabricated in a manner that may surmount these obstacles and allow future device manufacturers and designers greater freedom and imagination. Once extended as an SOI fabrication method[13], SMME provides a unique solution to device isolation, allowing device manufacturers the means to rapidly converge upon physical limitations of semiconductor devices.

To illustrate these obstacles, a short description of field effect transistors (FETs) is given along with examples of current standard fabrication methods. The SMME solution to these obstacles will be left to subsequent chapters for detailed clarity and exploration.

An elaboration on bulk crystal characteristics is provided followed by discussion of surface and interfacial characteristics of thin films. The basic physics of bulk and surface phenomena of crystalline thin films are an essential context for the current investigation and proposed modeling aspects of the fabrication process.

The technological foundation upon which this research is derived, SMME, involves the rapid diffusion of atomic silicon through an aluminum bulk mediator film (i.e. a film that mediates the transport of material to a buried interface). Therefore, an elaborate presentation of the various components of this diffusion process are provided to complete the introduction of fundamental aspects of the current investigation.

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